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Apple hiring SoC Power Flow Methodology Engineer, Cupertino, California

SoC Power Flow Methodology Engineer

Apple

Cupertino, California
Posted 2 weeks ago

Qualifications

Education

Minimum requirement of a Bachelors Degree in a relevant field.

Responsibilities

Primary Duties

  • Deliver new automated solutions and capabilities for the Silicon Engineering Power team
  • Help with the architecture, implementation, and verification of new low-power design and verification flows
  • Craft the low-power methodologies across a wide variety of future technologies
  • Create flows and tools related to power analysis, optimization and verification
  • Communicate with the design team to answer questions about the materials and drive issues to resolution

Benefits & Perks

Benefits Package

  • Comprehensive medical and dental coverage
  • retirement benefits
  • a range of discounted products and free services
  • reimbursement for certain educational expenses including tuition

Required Skills

Technical Skills

Good understanding of VLSI designs and SOC design flowsStrong passion for scripting and applying low-power domain-specific knowledge to create new software solutionsStrong background with flow development and/or object-oriented language algorithm design such as Python / C++ / JavaSolid understanding and proven track record using modern software testing and development practicesKnowledge of Tcl / PerlExperience with EDA toolsGUI developmentLow-power concepts such as UPF and low-power design

Soft Skills

Good written/verbal communications skills

Full Job Description

SoC Power Flow Methodology Engineer
Cupertino, California, United States
Hardware

Do you love creating solutions for complex challenges? As part of the Low Power group within Silicon Technologies, you'll help deliver cutting-edge new technology and capabilities for low-power chip design that fuels Apple's next-generation chips! In this role, as a member of our dynamic group, you will be responsible for the development and enhancement of our low-power flows, providing designers new capabilities in terms of power domains unseen in previous chips, while working on highly visible products used by millions of people every day!

Description
As a Power Flow Methodology Engineer, you'll deliver new automated solutions and capabilities for the Silicon Engineering Power team to build chips that are more power efficient than ever before. You will help with the architecture, implementation, and verification of new low-power design and verification flows and help to craft the low-power methodologies across a wide variety of future technologies. The work involves creating flows and tools related to power analysis, optimization and verification which may be run as part of RTL construction/verification, synthesis, or P&R. Additional responsibilities include communicating with the design team to answer questions about the materials and drive issues to resolution.

Minimum Qualifications
Minimum requirement of a Bachelors Degree in a relevant field.

Preferred Qualifications
Good understanding of VLSI designs and SOC design flows.
Strong passion for scripting and applying low-power domain-specific knowledge to create new software solutions.
Strong background with flow development and/or object-oriented language algorithm design such as Python / C++ / Java.
Solid understanding and proven track record using modern software testing and development practices.
Good written/verbal communications skills are required.
Knowledge of Tcl / Perl, experience with EDA tools, GUI development, and/or low-power concepts such as UPF and low-power design is a plus.

Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $126,800 and $190,900, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.

Apple accepts applications to this posting on an ongoing basis.

How to Apply

Estimated Salary

$71
/ hour

Apple pays $71 for Hardware Engineer in Cupertino, California, with most salaries ranging from $46 to $113. Pay can vary based on role, experience, and local cost of living.

Median
$71
Low
$46
High
$113

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Figures represent approximate ranges and may vary based on experience, location, and other factors. For the most accurate information, please consult the employer directly. Contact us to suggest updates to this information.