Network Cluster Architect

• Data Center InfrastructureAustin, Texas, United States

The Data Center Hardware Engineering team is responsible for designing and deploying Apple's next-generation compute infrastructure at scale. Our team works on projects from early design conception through mass production, focusing on cluster-level network architecture, data hall power distribution, rack-level electrical systems, and server hardware design. This is a highly cross-functional organization that collaborates closely with mechanical engineering, power systems, software and firmware teams, silicon design, hardware validation, and reliability engineering to deliver high-performance, energy-efficient compute solutions that power Apple's services and AI/ML workloads.

We are seeking experienced Systems Architects who can think holistically about infrastructure challengesfrom the data center level down to individual componentsand drive technical innovation through data-driven analysis and executive-level communication. Come join us!

The Network Cluster Architect will be responsible for owning and advancing critical investigations spanning cluster-level network topology, hall-level power distribution, rack-level electrical systems, and server hardware electronics design. This role involves coordinating with cross-functional teams including electrical validation, software engineering, and hardware test teams to aggregate validation results and verifying design assumptions.

ResponsibilitiesSystem Architecture & Design: Define and model data center infrastructure solutions from computer architecture and performance perspectives, including cluster network architectures, rack configurations, and scale-out requirements for dense compute and AI/ML workloads.

Cross-Functional Collaboration: Collaborate with mechanical, electrical, thermal, power, networking, firmware, software, and datacenter infrastructure stakeholders to ensure performant and scalable deployments. Negotiate and balance competing priorities across multiple engineering teams.

Technical Investigation & Analysis: Drive ongoing technical investigations to close open items from previous design phases. Conduct performance analysis, power efficiency studies, signal integrity assessments, and network topology optimization. Synthesize data from multiple sources and develop detailed technical documentation.

Network Topology Design: Provide guidance on optimized network designs for large-scale AI/ML clusters, considering factors like bandwidth, latency, scalability, and cost. Influence networking hardware and software component selection including switches, adapters, interconnects, and protocols.

Electrical Systems Integration: Support electrical design, simulation, bringup, debug, and validation activities. Work with high-speed digital interfaces (PCIe, Ethernet, DDR), power conversion topologies, and signal/power integrity requirements.

GenAI-Powered Modeling & Automation: Leverage modern GenAI tools (ChatGPT, Claude, etc.) to build analytical models, automate workflows, develop validation scripts, and accelerate data analysis tasks.

Executive Communication: Present complex technical findings, trade-off analyses, and strategic recommendations to senior leadership. Develop functional specifications, procedures, and documentation for complex system integration. Influence product-level decisions at the highest organizational levels.

Mentoring & Leadership: Provide technical mentorship to junior engineers on best practices, data-driven processes, and systems-level thinking.

Minimum QualificationsBachelor's degree in Electrical Engineering, Computer Engineering, or related technical field

8

• years of relevant industry experience in hardware architecture, electrical engineering, network architecture, or data center infrastructure design

Strong EE fundamentals, grounded in a solid understanding of electromagnetics and first principles

Deep understanding of cluster and data hall level infrastructure, including network topology, power distribution systems, PDUs, busways, and electrical safety standards

Working knowledge of design and validation requirements for common digital interfaces: I2C/SMBus, SPI, JTAG, USB, PCIe, Ethernet (QSFP, OSFP), DDR Memory, storage interfaces

Experience with high-speed board design and can guide SI/PI simulations

Preferred QualificationsMaster's degree or Ph.D. in Electrical Engineering, Computer Engineering, or related field with 10

• years of relevant industry experience

Functional experience defining and deploying datacenter cluster networking architectures over highly dense mesh networks and interconnected nodes for AI/ML workloads

• Proven track record of deploying AI/ML experiences at scale in large-scale data centers with strong experience in modern ML architecture deployment
• Strong technical breadth across computer subsystem technologies: CPU, xPU, storage, memory, power delivery, high-speed networking, I/O, thermal management

Exposure to hyperscale data center environments and experience designing for high volume, high power, highly reliable and available systems

Familiarity with network cluster topologies for AI/ML workloads

Proven ability to coordinate with cross-functional teams to aggregate validation results and drive technical consensus

Strong systems-level thinking with ability to understand dependencies across cluster, hall, rack, and server levels

High-speed PCB design experience with 10

layer boards, including material selection and SI/PI simulation tools

Understanding of computer architecture and design tradeoffs, high-speed bus throughput and latency analysis, and interconnect fabric standards

Understanding of power efficiency optimization at scale and sustainability initiatives

Prior experience in mentoring engineers or leading technical teams in preferred

Superior written, verbal, and visual communication skills with demonstrated ability to present to executive leadership and influence strategic decisions