SoC Physical Design Methodology Engineer
Apple
San Jose, California
Posted 1 weeks ago
Qualifications
Education
BS
Responsibilities
Primary Duties
- perform various types of physical verification checks at the chip and block level
- collaborate with the CAD/Technology teams for flow bring up and validation
- work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout
- lead schedules and support cross-functional engineering efforts
- work on padring, bump, RDL design, and working with the package and floorplan teams
Experience Requirements
Required
3+ years of relevant industry experience.
3 years of experience
Required Skills
Technical Skills
physical verification flowsDRC/LVS/ANT/HVDRC signoff flowsfull-chip integration methodologyESD and macro placement design guidelinesdigital and analog mixed signal back-end verification checksscripting skills perl/python/tclMentor CalibreSynopsys ICV
Full Job Description
SoC Physical Design Methodology Engineer
Work Locations (2) Submit Resume
At Apple, we work every single day to craft products that enrich people's lives! Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining our group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, we will enable our customers to do all the things they love with their devices! In this highly visible role, you will be a part of a critical team responsible for physical verification of an SOC.
Description
As a member of our physical design team, you will perform various types of physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography) at the chip and block level. You will collaborate with the CAD/Technology teams for flow bring up and validation. We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout. You will lead schedules and support cross-functional engineering efforts. You will work on padring, bump, RDL design, and working with the package and floorplan teams.
Minimum Qualifications
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant. At Apple, we believe accessibility is a fundamental human right. You'll find that idea reflected in everything here in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong. Learn about accessibility in Apple's workplace. Learn about reasonable accommodations for job applicants. Apple accepts applications to this posting on an ongoing basis. Submit Resume Back to search results See all roles in Beaverton.
Work Locations (2) Submit Resume
At Apple, we work every single day to craft products that enrich people's lives! Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining our group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, we will enable our customers to do all the things they love with their devices! In this highly visible role, you will be a part of a critical team responsible for physical verification of an SOC.
Description
As a member of our physical design team, you will perform various types of physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography) at the chip and block level. You will collaborate with the CAD/Technology teams for flow bring up and validation. We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout. You will lead schedules and support cross-functional engineering efforts. You will work on padring, bump, RDL design, and working with the package and floorplan teams.
Minimum Qualifications
- BS and 3+ years of relevant industry experience.
- Experienced with physical verification flows such as DRC/LVS/ANT/HVDRC signoff flows and full-chip integration methodology
- Experience with ESD and macro placement design guidelines, digital and analog mixed signal back-end verification checks and methodology
- Knowledge of all aspects of ASIC physical design and physical verification checks
- Scripting skills perl/python/tcl to debug flow related issues and automate checks
- Experienced in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc.
- Tapeout experience with a track record of successful signoff
- Layout design experience is a plus
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant. At Apple, we believe accessibility is a fundamental human right. You'll find that idea reflected in everything here in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong. Learn about accessibility in Apple's workplace. Learn about reasonable accommodations for job applicants. Apple accepts applications to this posting on an ongoing basis. Submit Resume Back to search results See all roles in Beaverton.
How to Apply
$194
/ hour
Apple pays $194 for Electrical Engineer in San Jose, California, with most salaries ranging from $131 to $294. Pay can vary based on role, experience, and local cost of living.
Median
$194
Low
$131
High
$294
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