SoC Physical Design Engineer, PnR
We are seeking a seasoned Physical Design technical leader with deep expertise in high-performance & low-power design. In this highly visible role, you will work closely with cross-functional teams to come up with efficient chip and IP physical architecture taking into account physical design constraints early in the design cycle.

You will be responsible for all aspects of physical design implementation from RTL2GDS including PnR, bump/RDL, STA, physical verification, EMIR, sign-off. You will also collaborate to drive methodologies and "best-known methods" to streamline PD work and develop guidelines and checklists. You will be the primary technical contact for your focus area and are motivated to solve more challenging timing closure issues, area & power optimization, etc.
Minimum Qualifications

• Minimum BS and 10+ years of relevant industry experience

Preferred Qualifications

• Knowledgeable in partition level P&R implementation including floorplanning, clock & power distribution, timing closure, and physical & electrical verification
• Knowledge of PD construction & analysis flows and methodology
• Strong interpersonal skills
• Recent successful tapeouts in deep submicron technology
• Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ
• Shown ability to execute to stringent schedule & die size requirements
• Experienced in industry standard tools and understanding their capabilities and underlying algorithms

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