RFIC Layout EngineerSan Francisco Bay Area, California, United States

Hardware

The Wireless SoC Radio Team designs state-of-art highly energy efficient CMOS radios, from RF to bits. To deliver these radios, our team is responsible for the design of a wide range of RF, analog, and mixed-signal blocks from RF front-end amplifiers to data converters, including baseband filters, baseband and RF phase-locked loops, crystal oscillators, and bandgap references.

We are working on new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering.

DescriptionAs an RFIC Layout Designer, you will be a key member of a RFIC team, researching, designing and bringing the next-generation of wireless technologies into high-volume production in advanced CMOS technology nodes. In this role, you will work closely with the RFIC design team to layout and verify custom RF and analog IP for complex SoC products.

You will have a critical impact on developing Apple's state-of-the-art radios and getting them into hundreds of millions of products.

ResponsibilitiesDetailed transistor-level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO.

Block level layout through full verification flow including extraction, DRC, LVS, and DFM checking.

Co-work with designers on block level floorplanning.

Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling.

Minimum Qualifications5

• year minimum related experience required.

Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS.

High level proficiency in interpretation of CALIBRE DRC, ERC, LVS in FinFet Technology.

Knowledge of Cadence layout tools.

Preferred QualificationsKnowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing.

Solid understanding of RC delay, electromigration, and coupling.

Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD and WPE.

Excellent communication skills and able to work with cross-functional teams.

Scripting skills in PERL or SKILL.

Pay & BenefitsAt Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $44.57 and $79.18/hr, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.

Apple accepts applications to this posting on an ongoing basis.