Mixed Signal RTL Design Engineer
Apple
Cupertino, California
Posted 4 days ago
Qualifications
Education
Bachelor's of Science in Electric Engineering
Responsibilities
Primary Duties
- RTL coding of blocks specified by you or others for advanced mixed signal circuits
- Writing detailed design specification
- Collaboration with the system architect, circuit designers and design verification engineers
- Using formal tools like LINT, CDC, RDC to guarantee RTL quality
- Supporting design verification to ensure bug free silicon
- Working with the PD team for timing closure for your designs
- Supporting silicon bring up
Experience Requirements
Required
10+ years of relevant experience preferred
Benefits & Perks
Benefits Package
- Comprehensive medical and dental coverage
- retirement benefits
- a range of discounted products and free services
- reimbursement for certain educational expenses including tuition
Required Skills
Technical Skills
Deep knowledge of RTL designDeep knowledge of Verilog and System VerilogGood knowledge of Mixed signal conceptsGood knowledge of Algorithm developmentWorking experience with physical design teamsGood Knowledge of front-end tools (Verilog simulators, linters, clock domain crossing checkers)Good knowledge of synthesis, static timing, DFT is a plusGood knowledge of System-Verilog assertions, checkers and other design verification techniques are a plusGood knowledge of scripting languages. Perl and Python are plusses.
Soft Skills
Good communication and presentation skills
Full Job Description
Mixed Signal RTL Design Engineer
Specify, design and help in the verification and lab bring up of advanced mixed-signal circuits (digital side).
Description
In this job, you will be responsible for RTL coding of blocks specified by you or others for advanced mixed signal circuits. You will be writing detailed design specification and will be in close collaboration with the system architect, circuit designers and design verification engineers. Formal tools like LINT, CDC, RDC will be used to guarantee RTL quality. Supporting design verification to ensure bug free silicon. Working with the PD team for timing closure for your designs and finally supporting silicon bring up.
Minimum Qualifications
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $184,700 and $324,800, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation.
Specify, design and help in the verification and lab bring up of advanced mixed-signal circuits (digital side).
Description
In this job, you will be responsible for RTL coding of blocks specified by you or others for advanced mixed signal circuits. You will be writing detailed design specification and will be in close collaboration with the system architect, circuit designers and design verification engineers. Formal tools like LINT, CDC, RDC will be used to guarantee RTL quality. Supporting design verification to ensure bug free silicon. Working with the PD team for timing closure for your designs and finally supporting silicon bring up.
Minimum Qualifications
- Bachelor's of Science in Electric Engineering with 10+ years of relevant experience preferred
- Deep knowledge of RTL design
- Deep knowledge of Verilog and System Verilog
- Good knowledge of Mixed signal concepts
- Good knowledge of Algorithm development
- Working experience with physical design teams
- Good Knowledge of front-end tools (Verilog simulators, linters, clock domain crossing checkers)
- Good knowledge of synthesis, static timing, DFT is a plus
- Good knowledge of System-Verilog assertions, checkers and other design verification techniques are a plus
- Good knowledge of scripting languages. Perl and Python are plusses.
- Good communication and presentation skills
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $184,700 and $324,800, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation.
How to Apply
$54
/ hour
Apple pays $54 for Engineer in Cupertino, California, with most salaries ranging from $33 to $88. Pay can vary based on role, experience, and local cost of living.
Median
$54
Low
$33
High
$88
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Figures represent approximate ranges and may vary based on experience, location, and other factors. For the most accurate information, please consult the employer directly. Contact us to suggest updates to this information.





