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Apple hiring SoC Physical Design Methodology Engineer, Beaverton, Oregon

SoC Physical Design Methodology Engineer

Apple

Beaverton, Oregon
Posted 1 weeks ago

Qualifications

Education

BS degree with 0 years of relevant industry experience.

Required Skills

Technical Skills

Experienced with physical verification flows such as DRC/LVS/ANT and layout integration methodologyUnderstands RTL to GDS physical design flowScripting skills to debug flow related issues and make enhancements as appropriateExperienced in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc.Layout design background and experience a plus

Full Job Description

SoC Physical Design Methodology Engineer
Work Locations (2) Submit Resume

At Apple, we work every single day to craft products that enrich people's lives! Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining our group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, we will enable our customers to do all the things they love with their devices! In this highly visible role, you will be a part of a critical team responsible for physical verification of an SOC.

As a member of our physical design team, you will perform various types of physical verification checks such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography at the chip and block level.

You will collaborate with the CAD/Technology teams for flow bring up and validation. We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout.

You will lead schedules and support cross-functional engineering efforts.

You will work on padring, bump, RDL design, and working with the package and floorplan teams.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant. At Apple, we believe accessibility is a fundamental human right. You'll find that idea reflected in everything here in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong. Learn about accessibility in Apple's workplace. Learn about reasonable accommodations for job applicants. Apple accepts applications to this posting on an ongoing basis.

Minimum Qualifications:
  • BS degree with 0 years of relevant industry experience.
Preferred Qualifications:
  • Experienced with physical verification flows such as DRC/LVS/ANT and layout integration methodology
  • Understands RTL to GDS physical design flow
  • Scripting skills to debug flow related issues and make enhancements as appropriate
  • Experienced in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc.
  • Layout design background and experience a plus

How to Apply

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