Primary Duties

• Develop and execute formal verification strategies using JasperGold and/or QuestaFormal for property checking (FPV), connectivity checking (CC), register verification, and sequential equivalence checking (SEQ)
• Write, review, and debug SystemVerilog Assertions (SVA) — including assumptions, assertions, and cover properties — to verify complex modem SoC design behaviors across NOC, interconnect, modem IPs and control logic
• Drive convergence on formal proofs by applying abstraction techniques, complexity reduction strategies, and assume-guarantee reasoning
• Collaborate with RTL designers, architects, and simulation-based DV engineers to define verification plans that incorporate formal methods alongside UVM-based simulation and emulation approaches
• Champion a 'formal-first' verification strategy by identifying and pursuing opportunities to apply formal verification to new design blocks — building on our established formal verification checklist deployed across SoC and NoC partitions
• Develop reusable formal verification infrastructure, including constraint libraries, parameterized property templates, and automated regression flows integrated into our CI/CD verification pipeline
• Contribute to coverage closure strategies by leveraging formal coverage analysis to complement simulation-driven functional coverage
• Mentor and guide DV engineers in formal verification techniques, SVA best practices, and proof convergence strategies
• Partner with EDA vendors to evaluate new formal verification capabilities and drive tool improvements that benefit the team